FIG. 1 illustrates a conventional Read-Only Memory (ROM) 50. During a read action, a column multiplexer 12 is actuated by way of a control device 30 such that on one hand a virtual voltage supply line 4 assigned to the corresponding column is charged to VDD and on the other a bit line 6 assigned to the corresponding column is no longer connected to VSS. Accordingly, to do this an input of a corresponding charging device or of an inverter 1 is set from 1 to 0. As a result, virtual voltage supply line 4 connected to the output is charged to VDD and a connection between bit line 6 and VSS is simultaneously interrupted via a precharging device or an inverter 7 and an NFET transistor 2. If corresponding word line 8 is then activated, information from a memory cell of memory device 50, which is defined by the column selected and word line 8, is read out by way of bit line 6.
A virtual voltage supply line is understood here to be a line that supplies memory cells with voltage. Since only the memory cell or memory cells which are directly involved in a read action (or write action) have to be supplied with voltage, the voltage supply of the memory cells is frequently capable of being switched (off) for energy-saving reasons. This means that only those voltage supply lines that supply voltage to the memory cell(s) which are directly involved in a read action (or write action) (e.g., all memory cells of a column in memory device 50) are switched on, while all other voltage supply lines are switched off. These switchable voltage supply lines are termed virtual voltage supply lines.
Since conventionally charging of virtual voltage supply line 4 and disconnection of bit line 6 from VSS takes place almost simultaneously, the stray electric coupling (also referred to as cross coupling) between virtual voltage supply line 4 and bit line 6 leads to bit line 6 being drawn towards potential VDDto which virtual voltage supply line 4 is charged. In other words, switching of the memory cells' voltage supply leads to an undesirable potential change in bit line 6 due to the electric coupling. FIG. 5A illustrates a potential curve of virtual voltage supply line 4 and bit line 6 for the conventional memory device of FIG. 1. A potential curve of a short virtual voltage supply line 4 is indicated at 31. A potential curve of a comparatively long virtual voltage supply line 4 is indicated at 32. As illustrated by a potential curve 33 of a bit line precharging signal, which corresponds to an output signal 20 of inverter 7, the potential curve of this bit line precharging signal is independent of whether bit line 6 is long or short or whether it is coupled to a long or short virtual voltage supply line 4. Thus, the potential of bit line 6 is likewise drawn to VDD by charging of virtual voltage supply line 4 to VDD, whereby this effect occurs more strongly with a long bit line 6 if the electric coupling between the bit line and virtual voltage supply line 4 is greater than is the case with a short bit line 6. This is also illustrated in FIG. 5Aa by a potential curve 34 for a short bit line 6 and potential curve 35 for a long bit line 6. In other words, the conventional time control of the deactivation of the bit line's precharging device is typically independent of the memory device's dimensions.
For these and other reasons, there is a need for the present invention.